LSI Process (Wafer)
MegaChips offers a wide range of wafer processes. We have established various design environments and flows based on our world-leading foundry partners.
We support varied logic processes, from an 8-inch legacy process to a leading-edge process, to meet diverse needs. In addition, at foundry partners we fulfill customer demands using a wide array of process options, such as MS/RF*, Embedded NVM*, BCD*, FD-SOI*, and Analog.
*MS/RF: Mixed Signal/Radio Frequency
*Embedded NVM: Embedded Non-Volatile Memory
*BCD: Bipolar CMOS DMOS
*FD-SOI: Fully-Depleted Silicon-On-Insulator technology
LSI Process (Packaging)
As a pioneer of the world’s fabless ASIC sector, MegaChips has provided packaging services over the past three decades in strong cooperation with leading Outsourced Assembly and Test (OSAT) companies.
We have established our own quality management methods based on our long experience with OSAT management and our close communications with them, providing high-quality and reliable packaging solutions that meet customer needs.
We provide optimal solutions by leveraging our large variety of packaging lineups.
|Type||LQFP/TQFP/QFP||Exposed LQFP/TQFP||Exposed VQFN||Multi Row QFN|
|Package size (mm)||7 x 7 ~ 28 x 28||7 x 7 ~ 28 x 28||4 x 4 ~ 12 x 12||9 x 9 ～ 13 x 13|
|Pin count||64 ~ 256||64 ~ 256||24 ~ 88||116 ~ 233|
|Pin pitch (mm)||0.4, 0.5||0.4, 0.5||0.4, 0.5||0.85|
|Package size (mm)||23 x 23 ~ 40 x 40||27 x 27 ~ 40 x 40||5.0 x 4.4 ~ 19 x 19||3.868 x 3.868|
|Pin count||233 ~ 1296||324 ~ 929||48 ~ 529||70|
|Pin pitch (mm)||1.0, 1.27||1.0, 1.27||0.4 ~ 0.8||0.4|
|Package size (mm)||27 x 27 ~ 42.5 x 42.5||9 x 9||13.5 x 13.5||-|
|Pin count||620 ~ 1760||49||776||-|
|Pin pitch (mm)||1.0, 1.27||1.0||0.57||-|
（Side by Side）
|Package||TFBGA, LFBGA, BGA, HSBGA, HFCBGA||VFBGA, TFBGA, LFBGA, LBGA, BGA, HSBGA||FBGA||Exposed TQFP64～,
|MP||Oct. 2004〜||Oct. 2005〜||Jan. 2004〜||Oct. 2007〜||Dec. 2012〜|
We reduce development time by collaborating with partners and utilizing their LSI/IP. For customer issues, we provide optimal solutions based on the breadth of our experience in semiconductor product development.