LPB Co-Design

MegaChips supports ASIC development based on the co-design flow as a method to ensure that the system operates reliably and normally.
Recent advances in faster transfer rates and the complexity of mounting technology have made it difficult to operate the system normally only by optimizing the package design. Therefore, LPB co-designs that optimize LSI, the package, and the circuit board as a whole are required. We are building an integrated analysis flow that utilizes the latest CAE tool to optimize the entire process.

Support for Co-Design

• Performing a cooperative analysis from the viewpoints of SIPI, thermal, and stresses in parallel with the design flow of the chip, package, and printed circuit board enables front loading (Identifies problems from the early stages of development and implements countermeasures).
• Achieving QCD optimization in the customers’ system with quality (reduce remakes and enhance system quality), cost (decrease components and workload), and delivery (shorten system development period).
• Providing a SPICE netlist, IBIS model (including an AMI), package model, and power supply model in response to customer demand for analysis.

Achieve Reliable and Stable Operation

The following are factors that make it difficult for customers to optimize their overall design:

• Reduced timing margins due to faster transmission rates (greater than 1Gbps)
• Significant effects of the SSN and Xtalk due to increased bit counts
• Reduced acceptable noise margins due to low voltage
• Building a thermal analysis model that takes into consideration the chip operating condition is necessary
• Timely feedback on thermal and stress analysis values to the chip package design is required

The cooperative analysis method of our chip, package, and printed circuit board enables the solving of these problems and achieves more reliable and stable operating conditions.

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